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  1. 会議・講演資料

CMOS標準ロジックを用いた確率的フラッシュ型AD変換器の試作と評価

https://kitami-it.repo.nii.ac.jp/records/8619
503495f1-8fb9-43ef-9a50-55a973485b0c
名前 / ファイル ライセンス アクション
ECT-14-58.pdf ECT-14-58 (602.1 kB)
Item type 会議発表論文 / Conference Paper(1)
公開日 2018-02-13
タイトル
言語 ja
タイトル CMOS標準ロジックを用いた確率的フラッシュ型AD変換器の試作と評価
タイトル
言語 en
タイトル Design and evaluation of stochastic flash ADC using standard CMOS logic
言語
言語 jpn
キーワード
言語 ja
主題Scheme Other
主題 確率的フラッシュ型ADC
キーワード
言語 ja
主題Scheme Other
主題 CMOSインバータ
キーワード
言語 ja
主題Scheme Other
主題 オフセットばらつき
キーワード
言語 ja
主題Scheme Other
主題 CMOS標準ロジック
キーワード
言語 en
主題Scheme Other
主題 stochastic fiash ADC
キーワード
言語 en
主題Scheme Other
主題 CMOS inverter
キーワード
言語 en
主題Scheme Other
主題 Offset variation,standard CMOS logic
資源タイプ
資源 http://purl.org/coar/resource_type/c_5794
タイプ conference paper
アクセス権
アクセス権 open access
アクセス権URI http://purl.org/coar/access_right/c_abf2
著者 竹端, 久登

× 竹端, 久登

WEKO 89909

ja 竹端, 久登

Search repository
谷本, 洋

× 谷本, 洋

WEKO 220
KAKEN - 研究者検索 20322886

ja 谷本, 洋

Search repository
吉澤 , 真吾

× 吉澤 , 真吾

WEKO 298
KAKEN - 研究者検索 20447080

ja 吉澤 , 真吾

Search repository
抄録
内容記述タイプ Abstract
内容記述 Since stochastic flash AD converters (SFADC) use statistical method,threshold voltages of SFADC are defined by comparator offsets instead of fixed interval reference voltages. SFADC needs many comparators. We designed and evaluated an experimental SFADC by using standard CMOS logic ICs to explore issues due to relatively small number of comparators (90 comparators) are used.
書誌情報 電気学会研究会資料. ECT, 電子回路研究会

巻 ECT-14, 号 58, p. 37-42, 発行日 2014
権利
権利情報 c2014 by IEEJ
著者版フラグ
値 publisher
出版者
出版者 一般社団法人 電気学会
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