{"created":"2021-03-01T06:00:57.140524+00:00","id":8619,"links":{},"metadata":{"_buckets":{"deposit":"1f48745a-030c-458d-b24c-b632ca982eee"},"_deposit":{"id":"8619","owners":[],"pid":{"revision_id":0,"type":"depid","value":"8619"},"status":"published"},"_oai":{"id":"oai:kitami-it.repo.nii.ac.jp:00008619","sets":["10"]},"author_link":["89909","220","298"],"item_5_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2014","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"58","bibliographicPageEnd":"42","bibliographicPageStart":"37","bibliographicVolumeNumber":"ECT-14","bibliographic_titles":[{"bibliographic_title":"電気学会研究会資料. ECT, 電子回路研究会"}]}]},"item_5_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Since stochastic flash AD converters (SFADC) use statistical method，threshold voltages of SFADC are defined by comparator offsets instead of fixed interval reference voltages. SFADC needs many comparators. We designed and evaluated an experimental SFADC by using standard CMOS logic ICs to explore issues due to relatively small number of comparators (90 comparators) are used.","subitem_description_type":"Abstract"}]},"item_5_publisher_32":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"一般社団法人 電気学会"}]},"item_5_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"c2014 by IEEJ"}]},"item_5_select_15":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_select_item":"publisher"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"竹端, 久登","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"89909","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"谷本, 洋","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"220","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"20322886","nameIdentifierScheme":"KAKEN - 研究者検索","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000020322886/"}]},{"creatorNames":[{"creatorName":"吉澤 , 真吾","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"298","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"20447080","nameIdentifierScheme":"KAKEN - 研究者検索","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000020447080/"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-02-13"}],"displaytype":"detail","filename":"ECT-14-58.pdf","filesize":[{"value":"602.1 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"ECT-14-58","url":"https://kitami-it.repo.nii.ac.jp/record/8619/files/ECT-14-58.pdf"},"version_id":"39bfa450-0f25-46bb-89af-fe9339e62d3a"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"確率的フラッシュ型ADC","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"CMOSインバータ","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"オフセットばらつき","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"CMOS標準ロジック","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"stochastic fiash ADC","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"CMOS inverter","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Offset variation，standard CMOS logic","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"conference paper","resourceuri":"http://purl.org/coar/resource_type/c_5794"}]},"item_title":"CMOS標準ロジックを用いた確率的フラッシュ型AD変換器の試作と評価","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"CMOS標準ロジックを用いた確率的フラッシュ型AD変換器の試作と評価","subitem_title_language":"ja"},{"subitem_title":"Design and evaluation of stochastic flash ADC using standard CMOS logic","subitem_title_language":"en"}]},"item_type_id":"5","owner":"1","path":["10"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2018-02-13"},"publish_date":"2018-02-13","publish_status":"0","recid":"8619","relation_version_is_last":true,"title":["CMOS標準ロジックを用いた確率的フラッシュ型AD変換器の試作と評価"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2022-12-13T02:23:53.579416+00:00"}