{"_buckets": {"deposit": "0f1ffa10-556f-470c-86ed-9d500d880cd2"}, "_deposit": {"id": "8583", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "8583"}, "status": "published"}, "_oai": {"id": "oai:kitami-it.repo.nii.ac.jp:00008583", "sets": ["10"]}, "item_5_biblio_info_6": {"attribute_name": "\u66f8\u8a8c\u60c5\u5831", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2010-03-25", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "33", "bibliographicPageEnd": "22", "bibliographicPageStart": "17", "bibliographicVolumeNumber": "ECT-10", "bibliographic_titles": [{"bibliographic_title": "\u96fb\u6c17\u5b66\u4f1a\u7814\u7a76\u4f1a\u8cc7\u6599. ECT, \u96fb\u5b50\u56de\u8def\u7814\u7a76\u4f1a"}]}]}, "item_5_description_4": {"attribute_name": "\u6284\u9332", "attribute_value_mlt": [{"subitem_description": "A new low voltage operating fully differential CMOS OTA construction, which uses dual-input cascoded CMOS inverters, is proposed. The OTA is a two-stage configuration with dual-input cascoded CMOS inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path form the output terminals to one of the input terminals of cascoded CMOS inverters. The OTA has been designed and fabricated in a 0.15 \u03bcm triple-well CMOS process, in order to effectively reduce its threshould voltages by the bulk bias technique. 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