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カスコード型CMOSインバータを用いた全差動OTAの設計と評価
https://kitami-it.repo.nii.ac.jp/records/8583
https://kitami-it.repo.nii.ac.jp/records/85836b4ea523-dfbb-4a82-b32f-59004c6d2ad3
名前 / ファイル | ライセンス | アクション |
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ECT-10-33 (1.6 MB)
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2018-02-07 | |||||
タイトル | ||||||
言語 | ja | |||||
タイトル | カスコード型CMOSインバータを用いた全差動OTAの設計と評価 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Design and Evaluation of Fully Differentioal OTA Using Cascoded CMOS Inverters | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
言語 | ja | |||||
主題Scheme | Other | |||||
主題 | カスコード型CMOSインバータ | |||||
キーワード | ||||||
言語 | ja | |||||
主題Scheme | Other | |||||
主題 | 全差動OTA | |||||
キーワード | ||||||
言語 | ja | |||||
主題Scheme | Other | |||||
主題 | 同相除去回路 | |||||
キーワード | ||||||
言語 | ja | |||||
主題Scheme | Other | |||||
主題 | 高電圧利得 | |||||
キーワード | ||||||
言語 | ja | |||||
主題Scheme | Other | |||||
主題 | 低電圧動作 | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Cascoded CMOS Inverter | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Differential OTA | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Common-Mode Rejection Circuit | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | High Voltage Gain | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Low Voltage Operation | |||||
資源タイプ | ||||||
資源 | http://purl.org/coar/resource_type/c_5794 | |||||
タイプ | conference paper | |||||
アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
著者 |
矢澤, 和樹
× 矢澤, 和樹× 谷本, 洋× 原口, 大× YAZAWA, Kazuki× TANIMOTO, Hiroshi× HARAGUCHI, Masaru |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | A new low voltage operating fully differential CMOS OTA construction, which uses dual-input cascoded CMOS inverters, is proposed. The OTA is a two-stage configuration with dual-input cascoded CMOS inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path form the output terminals to one of the input terminals of cascoded CMOS inverters. The OTA has been designed and fabricated in a 0.15 μm triple-well CMOS process, in order to effectively reduce its threshould voltages by the bulk bias technique. The OTA successfully operated from 1 V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption. | |||||
書誌情報 |
電気学会研究会資料. ECT, 電子回路研究会 巻 ECT-10, 号 33, p. 17-22, 発行日 2010-03-25 |
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権利 | ||||||
権利情報 | c2010IEEJapan | |||||
著者版フラグ | ||||||
値 | publisher | |||||
出版者 | ||||||
出版者 | 一般社団法人 電気学会 |