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VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems
https://kitami-it.repo.nii.ac.jp/records/7958
https://kitami-it.repo.nii.ac.jp/records/7958d4cfa34b-4289-4a7d-a1d3-4abf6b8af470
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
2015_3_IEICE_Yoshizawa.pdf (2.1 MB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2015-09-07 | |||||
| タイトル | ||||||
| タイトル | VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | OFDM-IDMA | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | interference canceller | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | VLSI architecture | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| アクセス権 | ||||||
| アクセス権 | open access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
| 著者 |
YOSHIZAWA, Shingo
× YOSHIZAWA, Shingo× NOZAKI, Mai× TANIMOTO, Hiroshi |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 44844 | |||||
| 識別子Scheme | KAKEN | |||||
| 識別子URI | https://nrid.nii.ac.jp/ja/nrid/1000020447080 | |||||
| 識別子 | 20447080 | |||||
| 姓名 | 吉澤, 真吾 | |||||
| 言語 | ja | |||||
| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 41202 | |||||
| 姓名 | 野崎, 麻衣 | |||||
| 言語 | ja | |||||
| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 44845 | |||||
| 識別子Scheme | KAKEN | |||||
| 識別子URI | https://nrid.nii.ac.jp/ja/nrid/1000020322886 | |||||
| 識別子 | 20322886 | |||||
| 姓名 | 谷本, 洋 | |||||
| 言語 | ja | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition. | |||||
| 書誌情報 |
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 巻 E98.A, 号 3, p. 811-819, 発行日 2015-03 |
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| DOI | ||||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | http://doi.org/10.1587/transfun.E98.A.811 | |||||
| 権利 | ||||||
| 権利情報 | c 2015 The Institute of Electronics, Information and Communication Engineers | |||||
| 出版者 | ||||||
| 出版者 | The Institute of Electronics, Information and Communication Engineers(一般社団法人電子情報通信学会 ) | |||||
| 言語 | en | |||||
| 関連サイト | ||||||
| URL | https://search.ieice.org/ | |||||
| 著者版フラグ | ||||||
| 言語 | en | |||||
| 値 | publisher | |||||
| 出版タイプ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
