| Item type |
学術雑誌論文 / Journal Article(1) |
| 公開日 |
2015-08-21 |
| タイトル |
|
|
タイトル |
A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions |
|
言語 |
en |
| 言語 |
|
|
言語 |
eng |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
FPGA |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
string matching |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
regular expression matching |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
bit-parallel algorithm |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
event stream processing |
| 資源タイプ |
|
|
資源 |
http://purl.org/coar/resource_type/c_6501 |
|
タイプ |
journal article |
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 著者 |
KANETA, Yusaku
YOSHIZAWA, Shingo
MINATO, Shin-ichi
ARIMURA, Hiroki
MIYANAGA, Yoshikazu
|
| 抄録 |
|
|
内容記述タイプ |
Abstract |
|
内容記述 |
In this paper, we propose a novel architecture for large-scale regular expression matching, called dynamically reconfigurable bit-parallel NFA architecture (Dynamic BP-NFA), which allows dynamic loading of regular expressions on-the-fly as well as efficient pattern matching for fast data streams. This is the first dynamically reconfigurable hardware with guaranteed performance for the class of extended patterns, which is a subclass of regular expressions consisting of union of characters and its repeat. This class allows operators such as character classes, gaps, optional characters, and bounded and unbounded repeats of character classes. The key to our architecture is the use of bit-parallel pattern matching approach, in which the information of an input non-deterministic finite automaton (NFA) is first compactly encoded in bit-masks stored in a collection of registers and block RAMs. Then, the NFA is efficiently simulated by a fixed circuitry using bitwise Boolean and arithmetic operations consuming one input character per clock regardless of the actual contents of an input text. Experimental results showed that our hardwares for both string and extended patterns were comparable to previous dynamically reconfigurable hardwares in their performances. |
| 書誌情報 |
en : IEICE TRANSACTIONS on Information and Systems
巻 E95-D,
号 7,
p. 1847-1857,
発行日 2012-07
|
| 権利 |
|
|
権利情報 |
c 2012 IEICE |
| 出版者 |
|
|
出版者 |
一般社団法人電子情報通信学会 |
|
言語 |
ja |
| 関連サイト |
|
|
URL |
http://search.ieice.org/index.html |
| 関連サイト |
|
|
URL |
http://search.ieice.org/bin/summary.php?id=e95-d_7_1847 |
| 著者版フラグ |
|
|
言語 |
en |
|
値 |
publisher |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
No144.pdf (718.3 kB)
