@inproceedings{oai:kitami-it.repo.nii.ac.jp:00008577, author = {矢澤, 和樹 and 小森山, 恵士 and 谷本, 洋 and YAZAWA, Kazuki and KOMORIYAMA, Keishi and TANIMOTO, Hiroshi}, book = {電気学会研究会資料. ECT, 電子回路研究会}, issue = {39}, month = {}, note = {There are strong demmands for low-voltage operating OPA/OTA in deep sub-micron CMOS processes. We have proposed a CMOS inverter based two-stage OTA configuration named FnI+FP OTA, which can operate 1 ~ 1.8 V of supply voltage, for 0.18 μm CMOS process. In this report, three series of fabrication results for the proposed F/F+F/B OTA configurations are presented with their design details. We have improved common-mode rqection ratio and voltage gain Over the prototype chip. The revised chip demonstrated 67 dB of voltage gain, unity frequency of 56 MHz, with 112 dB of CMRR, from 1.8 V of power supply with 3 mA of current consumption.}, pages = {13--18}, publisher = {一般社団法人 電気学会}, title = {CMOSインバータを用いた全差動OTAの試作と評価 : 高利得化の検討}, volume = {ECT-09}, year = {2009} }