@article{oai:kitami-it.repo.nii.ac.jp:00008270,
 author = {Shimazaki, Kosuke and Yoshizawa, Shingo and Hatakawa, Yasuyuki and Matsumoto, Tomoko and Konishi, Satoshi and Miyanaga, Yoshikazu},
 issue = {11},
 journal = {IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences},
 month = {Nov},
 note = {This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.},
 pages = {2114--2119},
 title = {A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing},
 volume = {E96A},
 year = {2013}
}