@article{oai:kitami-it.repo.nii.ac.jp:00007922, author = {Iwaizumi, Hiroki and Yoshizawa, Shingo and Miyanaga, Yoshikazu}, issue = {2013}, journal = {VLSI Design}, month = {}, note = {A processor design for singular value decomposition (SVD) and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP) architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs) and arithmetic instructions specialized in complex matrix operations.}, pages = {Article ID 625019--10 pages}, title = {A High-speed and Low-energy-consumption Processor for SVD-MIMO-OFDM Systems}, volume = {2013}, year = {2013} }