2024-03-29T12:08:47Z
https://kitami-it.repo.nii.ac.jp/oai
oai:kitami-it.repo.nii.ac.jp:00008619
2022-12-13T02:23:53Z
10
CMOS標準ロジックを用いた確率的フラッシュ型AD変換器の試作と評価
Design and evaluation of stochastic flash ADC using standard CMOS logic
竹端, 久登
89909
谷本, 洋
220
20322886
吉澤 , 真吾
298
20447080
確率的フラッシュ型ADC
CMOSインバータ
オフセットばらつき
CMOS標準ロジック
stochastic fiash ADC
CMOS inverter
Offset variation,standard CMOS logic
Since stochastic flash AD converters (SFADC) use statistical method,threshold voltages of SFADC are defined by comparator offsets instead of fixed interval reference voltages. SFADC needs many comparators. We designed and evaluated an experimental SFADC by using standard CMOS logic ICs to explore issues due to relatively small number of comparators (90 comparators) are used.
conference paper
一般社団法人 電気学会
2014
application/pdf
電気学会研究会資料. ECT, 電子回路研究会
58
ECT-14
37
42
https://kitami-it.repo.nii.ac.jp/record/8619/files/ECT-14-58.pdf
jpn
c2014 by IEEJ
open access