2024-03-28T16:15:59Z
https://kitami-it.repo.nii.ac.jp/oai
oai:kitami-it.repo.nii.ac.jp:00008270
2022-12-13T02:22:40Z
1:87
A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing
Shimazaki, Kosuke
Yoshizawa, Shingo
Hatakawa, Yasuyuki
Matsumoto, Tomoko
Konishi, Satoshi
Miyanaga, Yoshikazu
multi-user MIMO
Tomlinson-Harashima precoding
LQ decomposition
interference cancellation
This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.
journal article
Institute of Electronics, Information and Communication Engineers
2013-11
application/pdf
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
11
E96A
2114
2119
https://kitami-it.repo.nii.ac.jp/record/8270/files/2013_A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing.pdf
eng
http://doi.org/10.1587/transfun.E96.A.2114
c 2013 The Institute of Electronics, Information and Communication Engineers