2024-03-28T22:17:36Z
https://kitami-it.repo.nii.ac.jp/oai
oai:kitami-it.repo.nii.ac.jp:00007958
2022-12-13T02:21:11Z
1:87
VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems
YOSHIZAWA, Shingo
NOZAKI, Mai
TANIMOTO, Hiroshi
open access
c 2015 The Institute of Electronics, Information and Communication Engineers
OFDM-IDMA
interference canceller
VLSI architecture
Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition.
The Institute of Electronics, Information and Communication Engineers(一般社団法人電子情報通信学会 )
2015-03
eng
journal article
VoR
https://kitami-it.repo.nii.ac.jp/records/7958
http://doi.org/10.1587/transfun.E98.A.811
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E98.A
3
811
819
https://kitami-it.repo.nii.ac.jp/record/7958/files/2015_3_IEICE_Yoshizawa.pdf
application/pdf
2.1 MB
2016-11-22